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algebraic_circuits
First self-contained reference guide to algebraic circuits
by Antonio Lloris, Encarnación Castillo,Luis Parrilla and Antonio García
Springer
ISBN 978-3-642-54648-8 (hardcover)
ISBN 978-3-642-54649-5 (eBook)

 

2017

 


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2016

 


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2015


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2014


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2013


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2012


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2011


Conferences


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2010


Conferences


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2009


Conferences


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2008

      Journals

      • G. Botella, M. Rodríguez, A. García and E. Ros, "Neuromorphic Configurable Architecture for Robust Motion Estimation", International Journal of Reconfigurable Computing, vol. 2008, article ID 428265 (download PDF).
      • A. Martínez, M. A. Carvajal, D. P. Morales, A. García and A. J. Palma, "Development of a Electrical Capacitance Tomography System Using Four Rotating Electrodes", Sensors and Actuators A (Physical), vol. 148, no. 2, pp. 366-375 (download PDF).

Conferences

      • E. Castillo, L. Parrilla, A. García, U. Meyer-Baese and A. Lloris, "Watermarking techniques for soft core protection: automated tool advances and advantages", in Proc. of XXIII Conference on Design of Circuits and Integrated Systems DCIS'2008 (Grenoble, Nov. 12-14 2008).
      • E. Castillo, L. Parrilla, A. García, U. Meyer-Baese and A. Lloris, "Intellectual Property Protection of IP cores at HDL Design Level with Automatic Signature Spreading", in Proc. of International Conference on Advances in Electronics and Micro-electronics ENICS'2008 (Valencia, Sep. 29-Oct. 4 2008) (download PDF).
      • D. P. Morales, A. García, A. J. Palma, M.A. Carvajal, E. Castillo and L.F. Capitán-Vallvey, "Enhancing ADC Resolution through Field Programmable Analog Array Reconfiguration ," Proc. of 18th International Conference on Field Programmable Logic and Applications FPL'2008 (Heidelberg, Sep. 8-10 2008), pp. 635-638 (download PDF).
      • E. Castillo, U. Meyer-Baese, A. García, L. Parrilla and A. Lloris, “HDL-level automated watermarking of IP cores ”, Proc. SPIE Independent Component Analyses, Wavelets, Unsupervised Nano-Biometric Sensors and Neural Networks, vol. 6979, (Orlando FL, 16-18 Mar. 2008) (download PDF).
      • E. Castillo, L. Parrilla, A. García, U. Meyer-Baese, A. Lloris and G. Botella, "Automated Signature Insertion in Combinational Logic Pattern for HDL IP Core Protections," Proc. of 4th Southern Conference on Programmable Logic SPL'2008 (Bariloche, Mar. 26-28 2008), pp. 183-186 (download PDF).
      • G. Botella, E. Ros, M. Rodríguez, A. García, E, Castillo Morales, E. Andrés and M.C. Molina, "FPGA-Based Architecture for Robust Optical Flow Computation," Proc. of 4th Southern Conference on Programmable Logic SPL'2008 (Bariloche, Mar. 26-28 2008), pp. 1-6 (download PDF).

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2007

      Journals

      • E. Castillo, U. Meyer-Baese, A. García, L. Parrilla and A. Lloris, "IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 15 , pp. 578-591 (download PDF).

Conferences

      • E. Castillo, L. Parrilla, A. García, U. Meyer-Baese and A. Lloris, "Automated Signature Hosting for Soft Core Protection", Proc. of XXII Conference on Design of Circuits and Integrated Systems DCIS'2007 (Seville, Nov. 21-23 2007), pp. 470-475.
      • E. Castillo, L. Parrilla, A. García , U. Meyer-Baese and A. Lloris, "Intellectual Property Protection of HDL IP Cores through Automated Signature Hosting," Proc. of 17th International Conference on Field Programmable Logic and Applications FPL'2007 (Amsterdam, Aug. 27-29 2007), pp. 183-188 (download PDF).
      • D. P. Morales, A. García, A. J. Palma, A. Martínez-Olmos and E. Castillo , "Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing," Proc. of 17th International Conference on Field Programmable Logic and Applications FPL'2007 (Amsterdam, Aug. 27-29 2007), pp. 706-709 (download PDF).
      • E. Castillo, U. Meyer-Baese, A. García, L. Parrilla and A. Lloris, “Intellectual Property Protection of IP Cores Through High-Level Watermarking ”, Proc. SPIE Independent Component Analyses, Wavelets, Unsupervised Nano-Biometric Sensors and Neural Networks (Orlando FL, 10-13 Apr. 2007), vol. 6576, pp. 657519-1-10 (download PDF).
      • E. Castillo, U. Meyer-Baese, A. García, L. Parrilla, D. P. Morales and A. Lloris, "Digital Signature Embedding Technique for IP Core Protection ," Proc. of 3rd Southern Conference on Programmable Logic SPL'2007 (Mar del Plata, Feb. 26-28 2007), pp. 143-148 (download PDF).
      • D. P. Morales, A. García, A. J. Palma and A. Martínez-Olmos, "Merging FPGA and FPAA Reconfiguration Capabilities for IEEE 1451.4 Compliant Smart Sensor Applications ," Proc. of 3rd Southern Conference on Programmable Logic SPL'2007 (Mar del Plata, Feb. 26-28 2007), pp. 217-220 (download PDF).

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2006

      Journals

      • U. Meyer-Baese, H. Natarajan, E. Castillo and A. García, "Faster than the FFT: The chirp-z RAG-n Discrete Fast Fourier Transform", Frequenz, vol. 60, no. 7-8, pp. 147-151 (download PDF).

Conferences

      • E. Castillo, L. Parrilla, A. García, U. Meyer-Baese and A. Lloris, "HDL-level Watermarking Technique for IP Core Protection", in XXI Conference on Design of Circuits and Integrated Systems DCIS'2006 (Barcelona, Nov. 22-24 2006).
      • G. Botella, E. Ros, M. Rodríguez and A. García, "Bioinspired Robust Optical Flow in an FPGA System," ", Proc. of 9th EUROMICO Conference on Digital System Design DSD'2006 (Cavtat, Sep. 2006).
      • E. Castillo, U. Meyer-Baese, L. Parrilla, A. García and A. Lloris, "IPP Watermarking Technique for IP Core Protection on FPL Devices," Proc. of 16th International Conference on Field Programmable Logic and Applications FPL'2006 (Madrid, Aug. 28-30 2006), pp. 487-492 (download PDF).
      • E. Castillo, U. Meyer-Baese, A. García, L. Parrilla and A. Lloris, "RNS-Based Watermarking for IP Cores ," Proc. of 2nd Conference on Ph. D. Research in MicroElectronics and Electronics PRIME'2006 (Otranto, Jun. 12-16 2006), pp. 357-360 (download PDF).
      • G. Botella, E. Ros, M. Rodríguez, A. García and S. Romero, "Pre-processor for Bioinspired Optical Flow models: a Customizable Hardware Implementation," Proc. of 13th IEEE Mediterranean Electrotechnical Conference MELECOM’2006 (Benalmádena, May 16-18 2006), pp. 93-96 (download PDF).
      • U. Meyer-Baese, D. Sunkara, E. Castillo and A. García, “Custom Instruction Set NIOS-based OFDM Processor for FPGAs”, Proc. SPIE Wireless Sensing and Processing (Kissimmee FL, 14-18 Apr. 2006), vol. 6248, pp. 6248U-1-10 (download PDF).

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2005

      Journals

      • D. González, L.Parrilla, A. García, E. Castillo and A. Lloris, "Efficient Clock Distribution Scheme for VLSI RNS Enabled Controllers", Lecture Notes in Computer Science, vol. 3728, pp. 657-665 (download PDF).
      • J. Ramírez, U. Meyer-Baese and A. García, "Efficient RNS-based Design of Programmable FIR Filters Targeting FPL Technology," Journal of Circuits, Systems and Computers, vol. 14, no. 1, pp. 165-177, Feb. 2005 (download PDF).
      • U. Meyer-Baese, S. Rao, J. Ramírez and A. García, "Cost-effective Hogenauer Cascaded Integrator Comb Decimator Filter Design for Custom ICs," Electronics Letters, vol. 41, no. 3, pp. 158-160, Feb. 2005 (download PDF).

Conferences

      • E. Castillo, U. Meyer-Baese, L. Parrilla, A. García and A. Lloris, "RNS-based Watermarking Technique for IP Core Protection", in XX Conference on Design of Circuits and Integrated Systems DCIS'2005 (Lisbon, Nov. 23-25 2005).
      • E. Castillo, U. Meyer-Baese, L. Parrilla, A. García and A. Lloris, "Watermarking Strategies for RNS-based System Intellectual Property Protection", Proc. of 2005 IEEE Workshop on Signal Processing Systems SiPS'05 (Athens, Nov. 2-4 2005), pp. 160-165 (download PDF).
      • D. González, L.Parrilla, A. García, E. Castillo and A. Lloris, "Efficient Clock Distribution Scheme for VLSI RNS Enabled Controllers", in 15th International Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS'2005 (Leuven, Sep. 20-23 2005).

      • A. García, J. Ramírez, U. Meyer-Baese, E. Castillo and A. Lloris, "Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks," Proc. of 15th International Conference on Field Programmable Logic and Applications FPL'2005 (Tampere, Aug. 24-26 2005), pp. 531-534 (download PDF).

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    2004

      Journals

      • L. Parrilla, E. Castillo, A. García and A. Lloris, "Intellectual Property Protection for RNS Circuits on FPGAs," Lecture Notes in Computer Science, vol. 3203, pp. 1139-1141, Sep. 2004 (download PDF).
      • U. Meyer-Baese, S. Rao, J. Ramírez and A. García, "Area*Time Optimized Hogenauer Channelizer Design using FPL Devices," Lecture Notes in Computer Science, vol. 3203, pp. 384-393, Sep. 2004 (download PDF).

    Conferences

      • L. Parrilla, E. Castillo, A. García and A. Lloris, "Hiding Technique for Intellectual Property Protection on FPGAs", Proc. of XIX Conference on Design of Circuits and Integrated Systems DCIS'2004 (Bourdeaux, Nov. 24-26 2004), pp. 919-923.
      • J. Ramírez , U. Meyer-Baese and A. García, "Implementation of Polyphase RNS-based DWT Filter Banks with Efficient Embedded FPL Resource Utilization", Proc. of 2004 International Conference on Information Systems: New Generation ISGN'2004 (Las Vegas, Nov. 10-12 2004), pp. 67-72.

      • L. Parrilla, E. Castillo, A. García and A. Lloris, "Intellectual Property Protection for RNS Circuits on FPGAs," in 14th International Conference on Field Programmable Logic and Applications FPL'2004.

      • U. Meyer-Baese, S. Rao, J. Ramírez and A. García, "Area*Time Optimized Hogenauer Channelizer Design using FPL Devices," in 14th International Conference on Field Programmable Logic and Applications FPL'2004 (Antwerp, Aug. 30 - Sep. 1 2004).

      • J. Ramírez , U. Meyer-Baese and A. García, "Efficient Wavelet Architectures Using Field-Programmable Logic and Residue Number System Arithmetic", Proc. of 2004 SPIE AeroSense Conference (Orlando, Apr. 14-15 2004), pp. 222-232 (download PDF).

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    2003

      Journals

      • J. Ramírez, U. Meyer-Baese, A. García and A. Lloris, "Design and Implentation of RNS-based Adaptive Filters," Lecture Notes in Computer Science, vol. 2778, pp. 1135-1138, Sep. 2003 (download PDF) . 

      • J. Ramírez, U. Meyer-Baese, F. Taylor, A. García and A. Lloris, "Design and Implementation of High-performance RNS Wavelet Processors Using Custom IC Technologies," Journal of VLSI Signal Processing (Special Issue on Signal Processing Systems Part II), vol. 34, no. 3, pp. 227-237, Jul. 2003 (download PDF).

      • J. Ramírez, A. García, U. Meyer-Baese, F. Taylor and A. Lloris, "Implementation of RNS-based Distributed Arithmetic Discrete Wavelet Transform Architectures using Field-Programmable Logic," Journal of VLSI Signal Processing (Special Issue on Computer Arithmetic), vol. 33, no. 1-2, pp. 171-190, Feb. 2003 (download PDF).

      • J. Ramírez and A. García, "A Fast QRNS-based Algorithm for the DCT and its Field-Programmable logic Implementation," Journal of Circuits, Systems and Computers, vol. 12, no. 1, pp. 111-122, Feb. 2003 (download PDF).

      Conferences

      • D. González, A. García, G. A. Jullien, L. Parrilla, E. Castillo and A. Lloris, "Improved Clock Distribution Strategy for RNS-based DSP VLSI Systems", Proc. of XVIII Conference on Design of Circuits and Integrated Systems DCIS'2003 (Ciudad Real, Nov. 18-21 2003), pp. 256-260.
      • L. Parrilla, A. García, D. González, E. Castillo and A. Lloris, "Efficient Polyphase Architectures for DWT Computation using RNS over FPL Devices", Proc. of XVIII Conference on Design of Circuits and Integrated Systems DCIS'2003 (Ciudad Real, Nov. 18-21 2003), pp. 562-565.

      • J. Ramírez, U. Meyer-Baese, A. García and A. Lloris, "Design and Implementation of RNS-based Adaptive Filters", in 13th International Conference on Field Programmable Logic and Applications FPL'2003 (Lisbon, Sep. 1-3 2003).

      • U. Meyer-Baese, A. Meyer-Baese, J. Ramírez and A. García, "A High Radix CORDIC Architecture Dedicated to Compute the Gaussian Potential Function in Nueral Networks", Proc. of 2003 SPIE AeroSense Conference (Orlando, Apr. 21-22 2003), pp. 189-200 (download PDF).

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    2002

      Books & Book Chapters

      • D. González, A. García, G. A. Jullien, J. Ramírez, L. Parrilla and A. Lloris, "Clock Distribution in RNS-based VLSI Systems," in Advances in Systems Engineering: Signal Processing and Communications (N. Mastorakis, Ed.), pp. 323-328. Electrical and Computer Engineering Series, World Scientific and Engineering Society Press, 2002 (ISBN 960-8052-69-6).

      Journals

      • D. González, A. García, G. A. Jullien, J. Ramírez, L. Parrilla and A. Lloris, "A New Methodology for Efficient Synchronization of RNS-based VLSI Systems", Lecture Notes in Computer Science, vol. 2451, pp. 188-197, Sep. 2002 (download PDF).

      • U. Meyer-Baese, J. Ramírez and A. García, "Low Power High Speed Algebraic Integer Frequency Sampling Filter using FPLDs", Lecture Notes in Computer Science, vol. 2438, pp. 897-904, Sep. 2002 (download PDF).

      • J. Ramírez, A. García, U. Meyer-Baese and A. Lloris, "Fast RNS FPL-based Communications Receiver Design and Implementation," Lecture Notes in Computer Science, vol. 2438, pp. 472-481, Sep. 2002 (download PDF).

      • J. Ramírez, A. García, S. López-Buedo and A. Lloris, "RNS-enabled Digital Signal Processor Design", Electronics Letters, vol. 38, no. 6, pp. 266-268, Mar. 2002 (download PDF).

      Conferences

      • D. González, A. García, G. A. Jullien, J. Ramírez, L. Parrilla and A. Lloris, "A New Clock Distribution Strategy in RNS-based VLSI Systems", Proc. of XVII Conference on Design of Circuits and Integrated Systems DCIS'2002 (Santander, Nov. 19-22 2002), pp.175-180.

      • D. González, A. García, G. A. Jullien, J. Ramírez, L. Parrilla and A. Lloris, "A New Methodology for Efficient Synchronization of RNS-based VLSI Systems", in 12th International Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS'2002 (Seville, Sep. 11-13 2002).

      • U. Meyer-Baese, J. Ramírez and A. García, "Low Power High Speed Algebraic Integer Frequency Sampling Filter using FPLDs", in 12th International Conference on Field Programmable Logic and Applications FPL'2002 (Montpellier, Sep. 2-4 2002).

      • J. Ramírez, A. García, U. Meyer-Baese and A. Lloris, "Fast RNS FPL-based Communications Receiver Design and Implementation," in 12th International Conference on Field Programmable Logic and Applications FPL'2002 (Montpellier, Sep. 2-4 2002).

      • D. González, A. García, G. A. Jullien, J. Ramírez, L. Parrilla and A. Lloris, "Clock Distribution in RNS-based VLSI Systems," Proc. of 2002 WSEAS International Conference on Electronics and Hardware Systems IEHS'2002 (Chiclana, Jun. 12-16 2002), pp. 1511-1516 (download PDF).

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    2001

      Books & Book Chapters

      • P. G. Fernández, A. García, J. Ramírez, L. Parrilla and A. Lloris, "RNS Implementation of Two Dimensional Discrete Cosine Transform over FPL Devices," in Advances in Systems Science: Measurement, Circuits and Control (N. Mastorakis, Ed.), pp. 29-34. Electrical and Computer Engineering Series, World Scientific and Engineering Society Press, 2001 (ISBN 960-8052-39-4).

      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "A DCT Architecture based on Complex Residue Number System," in Advances in Signal Processing, Robotics and Communications (V. V. Kluev and N. Mastorakis, Eds.), pp. 9-14. Electrical and Computer Engineering Series, World Scientific and Engineering Society Press, 2001 (ISBN 960-8052-42-4).

      Journals

      • U. Meyer-Baese, A. García and F. Taylor, "Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic," Journal of VLSI Signal Processing, vol. 28, no. 1/2, pp. 115-128, May 2001 (download PDF).

      Conferences

      • L. Parrilla, J. Ramírez, A. García, P. G. Fernández and A. Lloris, "RNS-based PID Controllers with Adaptative Support over FPL Devices," Proc. of XVI Design of Circuits and Integrated Systems Conference DCIS'2001 (Porto, Nov. 21-24 2001), pp. 236-241.

      • J. Ramírez, P. G. Fernández, U. Meyer-Baese, F. Taylor, A. García and A. Lloris, "Index-based RNS-DWT Architectures for Custom IC Designs," Proc. of 2001 IEEE Workshop on Signal Processing Systems SiPS'2001 (Antwerp, Sep. 26-28 2001), pp. 70-79 (download PDF).

      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "A DCT Architecture based on Complex Residue Number System," in Proc. of WSES International Conference on Speech, Signal and Image Processing SSIP'2001 (Malta, Sep. 4-6 2001), pp. 2121-2126 (download PDF).

      • P. G. Fernández, J. Ramírez, A. García, L. Parrilla and A. Lloris, "Implementation of the One Dimensional Discrete Cosine Transform using the Residue Number System," Proc. of 8th IEEE International Conference on Electronics, Circuits and Systems ICECS'2001 (Malta, Sep. 2-5 2001), pp. 433-437 (download PDF).

      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "RNS-FPL merged Polyphase DWT Architectures," Proc. of 2001 European Conference on Circuit Theory and Design ECCTD'01 (Espoo, Aug. 28-31 2001).

      • P. G. Fernández, J. Ramírez, A. García, L. Parrilla and A. Lloris, "RNS Implementation of Two Dimensional Discrete Cosine Transform over FPL Devices," Proc. of 5th WSES Multiconference on Circuits, Systems, Communications and Computers CSCC'2001 (Rethymnon, Jul. 8-15 2001) (download PDF).

      • J. Ramírez, A. García, U. Meyer-Baese, F. Taylor, P. G. Fernández and A. Lloris, "Design of RNS-based Distributed Arithmetic DWT Filterbanks," Proc. of 2001 IEEE International Conference on Acoustics, Speech and Signal Processing ICASSP'2001 (Salt Lake City UT, May 7-11 2001), vol. 2, pp. 1193-1196 (download PDF).



    2000

      Books & Book Chapters

      • J. Ramírez, A. García, P. G. Fernández and A. Lloris, "FPL Implementation of a SIMD RISC RNS-enabled DSP," in Signal Processing, Communications and Computer Science (N. Mastorakis, Ed.), pp. 31-36. Electrical and Computer Engineering Series, World Scientific and Engineering Society Press, 2000 (ISBN 960-8052-18-1).

      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform," in Field Programmable Logic: The Roadmap to Reconfigurable Computing (R. W. Hartenstein and H. Gruenbacher, Eds.), pp. 342-351. Lecture Notes in Computer Science Series (vol. 1896), Springer Verlag, 2000 (ISBN 3-540-67899-9).

      Journals

      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "RNS-FPL Merged Architectures for the Orthogonal DWT," Electronics Letters, vol. 36, no. 14, pp. 1198-1199, Jul. 2000 (download PDF).

      Conferences

      • A. García, P. G. Fernández, L. Parrilla, J. Ramírez and A. Lloris, "RNS-Based Discrete PID Controllers with Efficient Conversion Schemes on FPL," Proc. of XV Design of Circuits and Integrated Systems Conference DCIS'2000 (Montpellier, Nov. 21-24 2000), pp. 258-263.

      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "A Novel QRNS-Based 1-D DCT Processor over Field-Programmable Logic," Proc. of XV Design of Circuits and Integrated Systems Conference DCIS'2000 (Montpellier, Nov. 21-24 2000), pp. 610-615.

      • P. G. Fernández, A. García, J. Ramírez, L. Parrilla and A. Lloris, "Fast RNS-Based DCT Computation with Fewer Multiplication Stages," Proc. of XV Design of Circuits and Integrated Systems Conference DCIS'2000 (Montpellier, Nov. 21-24 2000), pp. 276-281.

      • P. G. Fernández, A. García, J. Ramírez and A. Lloris, "A New RNS Architecture for the Computation of the Scaled 2D-DCT on Field-Programmable Logic," in 34th Asilomar Conference on Signals, Systems and Computers (Pacific Grove CA, Oct. 29 - Nov. 1 2000), pp. 379-383 (download PDF).

      • J. Ramírez, A. García, P. G. Fernández and A. Lloris,"Implementation of Canonical and Retimed RNS Architectures for the Orthogonal 1-D DWT over FPL Devices," in 34th Asilomar Conference on Signals, Systems and Computers (Pacific Grove CA, Oct. 29 - Nov. 1 2000), pp. 384-388 (download PDF).

      • P. G. Fernández, A. García, J. Ramírez and A. Lloris, "Fast RNS-Based 2D-DCT Computation on Field-Programmable Devices," Proc. of 2000 IEEE Workshop on Signal Processing Systems SiPS'2000 (Lafayette LA, Oct. 11-13 2000), pp. 365-373 (download PDF).

      • P. G. Fernández, A. García, J. Ramírez, L. Parrilla and A. Lloris, "Scaled 2D-DCT on Field-Programmable Devices Using the Residue Number System," Proc. of IASTED International Conference on Signal Processing and Communications SPC'2000 (Marbella, Sep. 19-22 2000), pp. 529-532.

      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "A High Performance Polyphase RNS-FPL Architecture for the Orthogonal 1-D DWT with Efficient Memory Allocation," Proc. of IASTED International Conference on Signal Processing and Communications SPC'2000 (Marbella, Sep. 19-22 2000), pp. 523-528.

      • A. García, J. Ramírez, L. Parrilla, P. G. Fernández and A. Lloris, "FPL Implementation of High-Performance PID Controllers," Proc. of IASTED International Conference on Signal Processing and Communications SPC'2000 (Marbella, Sep. 19-22 2000), pp. 519-522.

      • J. Ramírez, A. García, P. G. Fernández and A. Lloris, "An Efficient RNS Architecture for the Computation of Discrete Wavelet Transforms on Programmable Devices," Proc. of X European Signal Processing Conference EUSIPCO'2000 (Tampere, Sep. 5-8 2000), pp. 255-258 (download PDF).

      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform," Proc. of 10th International Conference on Field Programmable Logic and Applications FPL'2000 (Villach, Aug. 28-30 2000), pp. 342-351 (download PDF).

      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "Implementation of RNS Analysis and Synthesis Filter Banks for the Orthogonal Discrete Wavelet Transform over FPL Devices," in 43rd Midwest Symposium of Circuits and Systems MWSCAS'2000 (Lansing MI, Aug. 8-11 2000) (download PDF).

      • P. G. Fernández, A. García, J. Ramírez, L. Parrilla and A. Lloris, "A RNS-Based Matrix Vector Multiply FCT Architecture for DCT Computation," in 43rd Midwest Symposium of Circuits and Systems MWSCAS'2000 (Lansing MI, Aug. 8-11 2000) (download PDF).

      • J. Ramírez, A. García, P. G. Fernández and A. Lloris, "FPL Implementation of a SIMD RISC RNS-enabled DSP," Proc. of 4th World Multiconference on Circuits, Systems, Communications and Computers CSCC'2000 (Vouliagmeni, Jul. 10-15 2000), pp. 1281-1286.

      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "A New Architecture to Compute the Discrete Cosine Transform Using the Quadratic Residue Number System," Proc. of 2000 IEEE International Symposium on Circuits and Systems ISCAS'2000 (Geneva, May 28-31 2000), vol. 5, pp. 321-324 (download PDF).

      • L. Parrilla, A. García and A. Lloris, "Implementation of High Performance PID Controllers Using RNS and Field-Programmable Devices," Proc. of 2000 IFAC Workshop on Digital Control PID'00 (Terrassa, Apr. 5-7 2000), pp. 628-631.

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    1999

      Journals

      • A. García and G. A. Jullien, "Comments on 'An Arithmetic Free Parallel Mixed-Radix Conversion Algorithm'," IEEE Transactions on Circuits and Systems II-Analog and Digital Signal Processing, vol. 46, no. 9, pp. 1259-1260, Sep. 1999 (download PDF).

      • A. García and A. Lloris, "A Look-Up Scheme for Scaling in the RNS," IEEE Transactions on Computers, vol. 48, no.7, pp. 748-751, Jul. 1999 (download PDF).

      Conferences

      • L. Parrilla, A. García, A. Martínez, J. Ramírez and A. Lloris, "High-Performance RNS Pipelined PID Controllers Using Field-Programmable Devices," Proc. of XIV Design of Circuits and Integrated Systems Conference DCIS'99 (Palma de Mallorca, Nov. 16-19 1999), pp. 367-371 .

      • J. Ramírez, A. García, L. Parrilla, P. G. Fernández and A. Lloris, "A Novel RNS-Based SIMD RISC Processor for Digital Signal Processing," Proc. of 33rd Asilomar Conference on Signals, Systems and Computers, (Pacific Grove CA, Oct. 24-27 1999), vol. 2, pp. 1307-1311 (download PDF).

      • P. G. Fernández, A. García, J. Ramírez, L. Parrilla and A. Lloris, "A New Implementation of the Discrete Cosine Transform in the Residue Number System," Proc. of 33rd Asilomar Conference on Signals, Systems and Computers (Pacific Grove CA, Oct. 24-27 1999), vol 2, pp. 1302-1306 (download PDF).

      • A. García, U. Meyer-Baese, A. Lloris and F. J. Taylor, "RNS Implementation of FIR Filters Based on Distributed Arithmetic Using Field-Programmable Logic," Proc. of 1999 IEEE International Symposium on Circuits and Systems ISCAS'99 (Orlando FL, May 30-June 2 1999), vol. 1, pp. 486-489 (download PDF).

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    1998

      Conferences

      • A. García and A. Lloris, "RNS Scaling Based on Pipelined Multipliers for Prime Moduli," Proc. of 1998 IEEE Workshop on Signal Processing Systems SiPS'98 (Cambridge MA, Oct. 8-10 1998), pp. 459-468 (download PDF).

      • A. García and A. Lloris, "Pipelined RNS Multipliers: an Application to Scaling," Proc. of 5th IEEE International Conference on Electronics, Circuits and Systems ICECS'98 (Lisbon, Sep. 7-10 1998), vol. 3, pp. 55-58 (download PDF).

      • A. García, U. Meyer-Baese and F. J. Taylor, "Pipelined Hogenauer CIC Filters Using Field-Programmable Logic and Residue Number System," Proc. of 1998 IEEE International Conference on Acoustics, Speech and Signal Processing ICASSP'98 (Seattle WA, May 11-15 1998), vol. 5, pp. 3085-3088 (download PDF).

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    1997

      Conferences

      • A. García and A. Lloris, "A Scaling Scheme Based in Conventional RNS Arithmetical Circuits," Proc. of XII Design of Circuits and Integrated Systems Conference DCIS'97 (Seville, Nov. 1997), pp. 739-744.

      • A. García and A. Lloris, "Pipelined Submodular Isomorphic Mapped RNS Multipliers," Proc. of XII Design of Circuits and Integrated Systems Conference DCIS'97 (Seville, Nov. 1997), pp. 733-738.

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Dpto. Electrónica y Tecnología de Computadores

Facultad de Ciencias - Universidad de Granada 18071 - Granada

Mantenimiento: Antonio García Ríos

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