Departamento de Electrónica y Tecnología de Computadores

Publications

2018 | 2017 | 2016 | 2015 | 2014 | 2013 | 2012 | 2011 | 2010 | 2009 | 2008 | 2007 | 2006 | 2005 | 2004 | 2003 | 2002 | 2001 | 2000 | 1999 | 1998 | 1997

 

algebraic_circuits
First self-contained reference guide to algebraic circuits
by Antonio Lloris, Encarnación Castillo, Luis Parrilla and Antonio García
Springer
ISBN 978-3-642-54648-8 (hardcover)
ISBN 978-3-642-54649-5 (eBook)

 

2018

      Journals
      Conferences
      • V. Toral-López, S. Criado, F.J. Romero, D.P. Morales, E. Castillo, A. García, A. Tahmassebi and A. Meyer-Bäse, "Wearable biosignal acquisition system for decision aid", in Proc. SPIE, Smart Biomedical and Physiological Sensor Technology XV (Orlando FL, Apr. 15 2018), 106620F

 


2017

      Journals
      Conferences
      • D. P. Morales, E. Castillo, L. Parrilla, A. García and A. Otín, "Digital and analog reconfigurable technologies for reducing Waste of Electrical and Electronics Equipment", in XXXII Conference on Design of Circuits and Integrated Systems DCIS'2017 (Barcelona, Nov. 22-24 2017)

 


2016

      Journals

 


2015

      Journals
      Conferences

 

2014

      Books & Book Chapters
      • A. Lloris, E. Castillo, L. Parrilla and A. García, "Algebraic Circuits", Springer 2014 (ISBN 978-3-642-54648-8)
      Journals
      • V. U. Ruiz, E. Castillo, D. P. Morales, A. García, L. Parrilla, F. S. Molina, and J. Florido, "ECG processing on reconfigurable hardware for efficient artifact reduction", in Experimental & Clinical Cardiology, vol. 20, no. 8, pp 3023.3028
      Conferences

2013

      Journals
      Conferences
      • L. Parrilla, E. Castillo, D. P. Morales, A. García, J. Florido, F. S. Molina and A. J. Palma, "ECG wandering and noise removing in one step using wavelets", in XXVIII Conference on Design of Circuits and Integrated Systems DCIS'2013 (San Sebastián, Nov. 27-29 2013)

2012

      Journals

2011

      Journals
      • D. P. Morales , A. García, E. Castillo, U. Meyer-Baese and A. J. Palma, "Wavelets for full reconfigurable ECG acquisition system", in Proc. of SPIE Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and Nanoengineering, vol. 8058, (Orlando FL, 27-29 Apr. 2011), pp. 805817-1-805817-8

2010

      Journals
      • L. Parrilla, E. Castillo, A. García and E. Todorovich, "IPP Watermarking-based Protection of Embeeded Cores over FPGAs ", Proc. of XXV Conference on Design of Circuits and Integrated Systems DCIS'2010 (Lanzarote, Nov. 17-19 2010), pp. 631-636
      • L. Parrilla, E. Castillo, U. Meyer-Bäse, A. García, D. González, E. Todorovich, E. Boemo, and A. Lloris, "Watermarking strategies for IP protection of micro-processor cores", Proc. of SPIE Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and Nanoengineering, vol. 7703, (Orlando FL, 23 Apr. 2010), pp. 77030L-77030L-11

2009

      Journals
      • L. Parrilla, E. Castillo, A. García, E. Todorovich, D. González and A. Lloris, "Intellectual Property Protection of uP Cores ", Proc. of XXIV Conference on Design of Circuits and Integrated Systems DCIS'2009 (Zaragoza, Nov. 17-20 2009), pp. 315-320.
      • G. Botella, A. García, U. Meyer-Baese, M. Rodríguez, M. C. Molina, and L. Parrilla, “Enhanced Gradient-based Motion Vector Coprocessor”, Proc. 19th International Conference on Field Programmable Logic and Applications FPL'2009 (Prague, 3-6 Aug. 2009), pp. 687-690
      • E. Castillo, U. Meyer-Baese, A. García, L. Parrilla and A. Lloris, “New Advances for Automated IP soft-core Protection”, Proc. SPIE Independent Component Analyses, Wavelets, Neural Networks, Biosystems and Nanoengineering, vol. 7343, (Orlando FL, 13-17 Apr. 2009), pp. 73430L.1-73430L.12

2008

      Journals
      • E. Castillo, L. Parrilla, A. García, U. Meyer-Baese and A. Lloris, "Watermarking techniques for soft core protection: automated tool advances and advantages", in Proc. of XXIII Conference on Design of Circuits and Integrated Systems DCIS'2008 (Grenoble, Nov. 12-14 2008).
      • E. Castillo, U. Meyer-Baese, A. García, L. Parrilla and A. Lloris, “HDL-level automated watermarking of IP cores”, Proc. SPIE Independent Component Analyses, Wavelets, Unsupervised Nano-Biometric Sensors and Neural Networks, vol. 6979, (Orlando FL, 16-18 Mar. 2008

2007

      Journals
      • E. Castillo, L. Parrilla, A. García, U. Meyer-Baese and A. Lloris, "Automated Signature Hosting for Soft Core Protection", Proc. of XXII Conference on Design of Circuits and Integrated Systems DCIS'2007 (Seville, Nov. 21-23 2007), pp. 470-475.

2006

      Journals
      • E. Castillo, L. Parrilla, A. García, U. Meyer-Baese and A. Lloris, "HDL-level Watermarking Technique for IP Core Protection", in XXI Conference on Design of Circuits and Integrated Systems DCIS'2006 (Barcelona, Nov. 22-24 2006).
      • G. Botella, E. Ros, M. Rodríguez and A. García, "Bioinspired Robust Optical Flow in an FPGA System," ", Proc. of 9th EUROMICO Conference on Digital System Design DSD'2006 (Cavtat, Sep. 2006).
      • E. Castillo, U. Meyer-Baese, A. García, L. Parrilla and A. Lloris, "RNS-Based Watermarking for IP Cores," Proc. of 2nd Conference on Ph. D. Research in MicroElectronics and Electronics PRIME'2006 (Otranto, Jun. 12-16 2006), pp. 357-360

2005

      Journals
      • E. Castillo, U. Meyer-Baese, L. Parrilla, A. García and A. Lloris, "RNS-based Watermarking Technique for IP Core Protection", in XX Conference on Design of Circuits and Integrated Systems DCIS'2005 (Lisbon, Nov. 23-25 2005)
      • D. González, L.Parrilla, A. García, E. Castillo and A. Lloris, "Efficient Clock Distribution Scheme for VLSI RNS Enabled Controllers", in 15th International Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS'2005 (Leuven, Sep. 20-23 2005)

      Conferences
      • L. Parrilla, E. Castillo, A. García and A. Lloris, "Hiding Technique for Intellectual Property Protection on FPGAs", Proc. of XIX Conference on Design of Circuits and Integrated Systems DCIS'2004 (Bourdeaux, Nov. 24-26 2004), pp. 919-923
      • J. Ramírez , U. Meyer-Baese and A. García, "Implementation of Polyphase RNS-based DWT Filter Banks with Efficient Embedded FPL Resource Utilization", Proc. of 2004 International Conference on Information Systems: New Generation ISGN'2004 (Las Vegas, Nov. 10-12 2004), pp. 67-72
      • L. Parrilla, E. Castillo, A. García and A. Lloris, "Intellectual Property Protection for RNS Circuits on FPGAs," in 14th International Conference on Field Programmable Logic and Applications FPL'2004
      • U. Meyer-Baese, S. Rao, J. Ramírez and A. García, "Area*Time Optimized Hogenauer Channelizer Design using FPL Devices," in 14th International Conference on Field Programmable Logic and Applications FPL'2004 (Antwerp, Aug. 30 - Sep. 1 2004)
      Conferences
      • D. González, A. García, G. A. Jullien, L. Parrilla, E. Castillo and A. Lloris, "Improved Clock Distribution Strategy for RNS-based DSP VLSI Systems", Proc. of XVIII Conference on Design of Circuits and Integrated Systems DCIS'2003 (Ciudad Real, Nov. 18-21 2003), pp. 256-260
      • L. Parrilla, A. García, D. González, E. Castillo and A. Lloris, "Efficient Polyphase Architectures for DWT Computation using RNS over FPL Devices", Proc. of XVIII Conference on Design of Circuits and Integrated Systems DCIS'2003 (Ciudad Real, Nov. 18-21 2003), pp. 562-565
      • J. Ramírez, U. Meyer-Baese, A. García and A. Lloris, "Design and Implementation of RNS-based Adaptive Filters", in 13th International Conference on Field Programmable Logic and Applications FPL'2003 (Lisbon, Sep. 1-3 2003)
      Conferences
      • D. González, A. García, G. A. Jullien, J. Ramírez, L. Parrilla and A. Lloris, "A New Clock Distribution Strategy in RNS-based VLSI Systems", Proc. of XVII Conference on Design of Circuits and Integrated Systems DCIS'2002 (Santander, Nov. 19-22 2002), pp.175-180
      • D. González, A. García, G. A. Jullien, J. Ramírez, L. Parrilla and A. Lloris, "A New Methodology for Efficient Synchronization of RNS-based VLSI Systems", in 12th International Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS'2002 (Seville, Sep. 11-13 2002)
      • U. Meyer-Baese, J. Ramírez and A. García, "Low Power High Speed Algebraic Integer Frequency Sampling Filter using FPLDs", in 12th International Conference on Field Programmable Logic and Applications FPL'2002 (Montpellier, Sep. 2-4 2002)
      • J. Ramírez, A. García, U. Meyer-Baese and A. Lloris, "Fast RNS FPL-based Communications Receiver Design and Implementation," in 12th International Conference on Field Programmable Logic and Applications FPL'2002 (Montpellier, Sep. 2-4 2002)
      • D. González, A. García, G. A. Jullien, J. Ramírez, L. Parrilla and A. Lloris, "Clock Distribution in RNS-based VLSI Systems," Proc. of 2002 WSEAS International Conference on Electronics and Hardware Systems IEHS'2002 (Chiclana, Jun. 12-16 2002), pp. 1511-1516

    2001

      Books & Book Chapters
      • P. G. Fernández, A. García, J. Ramírez, L. Parrilla and A. Lloris, "RNS Implementation of Two Dimensional Discrete Cosine Transform over FPL Devices," in Advances in Systems Science: Measurement, Circuits and Control (N. Mastorakis, Ed.), pp. 29-34. Electrical and Computer Engineering Series, World Scientific and Engineering Society Press, 2001 (ISBN 960-8052-39-4).
      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "A DCT Architecture based on Complex Residue Number System," in Advances in Signal Processing, Robotics and Communications (V. V. Kluev and N. Mastorakis, Eds.), pp. 9-14. Electrical and Computer Engineering Series, World Scientific and Engineering Society Press, 2001 (ISBN 960-8052-42-4).
      Journals Conferences
      • L. Parrilla, J. Ramírez, A. García, P. G. Fernández and A. Lloris, "RNS-based PID Controllers with Adaptative Support over FPL Devices," Proc. of XVI Design of Circuits and Integrated Systems Conference DCIS'2001 (Porto, Nov. 21-24 2001), pp. 236-241.
      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "RNS-FPL merged Polyphase DWT Architectures," Proc. of 2001 European Conference on Circuit Theory and Design ECCTD'01 (Espoo, Aug. 28-31 2001).
      • J. Ramírez, A. García, U. Meyer-Baese, F. Taylor, P. G. Fernández and A. Lloris, "Design of RNS-based Distributed Arithmetic DWT Filterbanks," Proc. of 2001 IEEE International Conference on Acoustics, Speech and Signal Processing ICASSP'2001 (Salt Lake City UT, May 7-11 2001), vol. 2, pp. 1193-1196


    2000

      Books & Book Chapters
      • J. Ramírez, A. García, P. G. Fernández and A. Lloris, "FPL Implementation of a SIMD RISC RNS-enabled DSP," in Signal Processing, Communications and Computer Science (N. Mastorakis, Ed.), pp. 31-36. Electrical and Computer Engineering Series, World Scientific and Engineering Society Press, 2000 (ISBN 960-8052-18-1)
      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform," in Field Programmable Logic: The Roadmap to Reconfigurable Computing (R. W. Hartenstein and H. Gruenbacher, Eds.), pp. 342-351. Lecture Notes in Computer Science Series (vol. 1896), Springer Verlag, 2000 (ISBN 3-540-67899-9)
      Conferences
      • A. García, P. G. Fernández, L. Parrilla, J. Ramírez and A. Lloris, "RNS-Based Discrete PID Controllers with Efficient Conversion Schemes on FPL," Proc. of XV Design of Circuits and Integrated Systems Conference DCIS'2000 (Montpellier, Nov. 21-24 2000), pp. 258-263
      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "A Novel QRNS-Based 1-D DCT Processor over Field-Programmable Logic," Proc. of XV Design of Circuits and Integrated Systems Conference DCIS'2000 (Montpellier, Nov. 21-24 2000), pp. 610-615
      • P. G. Fernández, A. García, J. Ramírez, L. Parrilla and A. Lloris, "Fast RNS-Based DCT Computation with Fewer Multiplication Stages," Proc. of XV Design of Circuits and Integrated Systems Conference DCIS'2000 (Montpellier, Nov. 21-24 2000), pp. 276-281
      • P. G. Fernández, A. García, J. Ramírez, L. Parrilla and A. Lloris, "Scaled 2D-DCT on Field-Programmable Devices Using the Residue Number System," Proc. of IASTED International Conference on Signal Processing and Communications SPC'2000 (Marbella, Sep. 19-22 2000), pp. 529-532
      • J. Ramírez, A. García, P. G. Fernández, L. Parrilla and A. Lloris, "A High Performance Polyphase RNS-FPL Architecture for the Orthogonal 1-D DWT with Efficient Memory Allocation," Proc. of IASTED International Conference on Signal Processing and Communications SPC'2000 (Marbella, Sep. 19-22 2000), pp. 523-528
      • A. García, J. Ramírez, L. Parrilla, P. G. Fernández and A. Lloris, "FPL Implementation of High-Performance PID Controllers," Proc. of IASTED International Conference on Signal Processing and Communications SPC'2000 (Marbella, Sep. 19-22 2000), pp. 519-522
      • J. Ramírez, A. García, P. G. Fernández and A. Lloris, "FPL Implementation of a SIMD RISC RNS-enabled DSP," Proc. of 4th World Multiconference on Circuits, Systems, Communications and Computers CSCC'2000 (Vouliagmeni, Jul. 10-15 2000), pp. 1281-1286
      • L. Parrilla, A. García and A. Lloris, "Implementation of High Performance PID Controllers Using RNS and Field-Programmable Devices," Proc. of 2000 IFAC Workshop on Digital Control PID'00 (Terrassa, Apr. 5-7 2000), pp. 628-631

    1999

      Conferences
      • L. Parrilla, A. García, A. Martínez, J. Ramírez and A. Lloris, "High-Performance RNS Pipelined PID Controllers Using Field-Programmable Devices," Proc. of XIV Design of Circuits and Integrated Systems Conference DCIS'99 (Palma de Mallorca, Nov. 16-19 1999), pp. 367-371


    1997

      Conferences
      • A. García and A. Lloris, "A Scaling Scheme Based in Conventional RNS Arithmetical Circuits," Proc. of XII Design of Circuits and Integrated Systems Conference DCIS'97 (Seville, Nov. 1997), pp. 739-744
      • A. García and A. Lloris, "Pipelined Submodular Isomorphic Mapped RNS Multipliers," Proc. of XII Design of Circuits and Integrated Systems Conference DCIS'97 (Seville, Nov. 1997), pp. 733-738

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